Lead Design Engineer
Core
Lead Design Engineer responsible for RTL coding, datapath designs, complex FIFO design, and high-speed SerDes IP development.
Role type
Senior IC digital design engineer (SerDes/High-Speed Interfaces)
Builds
Complex SerDes IP blocks and high-speed digital circuits for various technology nodes
Domain
Semiconductor design, Digital Logic, High-Speed Interfaces
Required skills
RTL coding, datapath design, complex FIFO design, complete design flows (LINT, SDC, CDC, DFT, CLP, Synthesis, PnR), micro-architecture design, SerDes IP development, analog-digital co-design, signal processing IP integration
Preferred skills
USB, PCIe, MIPI (DPHY), HDMI/Display protocols, PLLs, dividers, calibration algorithms
Technologies
LINT, SDC, CDC, DFT, CLP, Synthesis, PnR, SerDes, USB, PCIe, MIPI, HDMI
Responsibilities
Design complex FIFOs and datapaths, collaborate with analog teams on algorithms and feedback loops, integrate signal processing IPs, perform rigorous pre-delivery checks
Seniority
Senior, hands-on IC
