Principal SoC RTL Engineer
Core
Own pre-tapeout quality for digital SoC modules on MCU platforms and drive architecture, microarchitecture, and RTL development for next-generation silicon.
Role type
Principal SoC RTL Engineer (IC)
Builds
Digital SoC modules and MCUs for wearables, medical devices, IoT, and AI edge applications
Domain
Semiconductor / SoC Design / Low-power MCU
Deliverable
production ML models | product features
Required skills
Verilog/SystemVerilog RTL development, SoC architecture design, 3rd-party IP integration, timing and power optimization, LINT/CDC/RDC analysis, silicon bring-up and validation
Preferred skills
Deep knowledge of sub- and near-threshold technologies, FPGA collaboration, physical design collaboration
Technologies
Verilog, SystemVerilog, LINT, CDC, RDC
Responsibilities
Develop Verilog/SystemVerilog RTL for complex IPs and SoCs; Evaluate and integrate 3rd-party IP; Partner with verification and FPGA teams on test planning and debug; Collaborate with physical design to hit timing and power targets; Run quality check tools (LINT, CDC, RDC) and fix/waive issues; Assist in silicon bring-up and validation
Seniority
Principal, hands-on IC
