ASIC Timing Engineer
Core
Driving timing analysis and closure for next-generation AI chips designed for specific model architectures.
Role type
ASIC Timing Engineer
Builds
High-performance AI chips (ASICs) optimized for transformers and deep reasoning models
Domain
Semiconductor hardware design / AI accelerators
Deliverable
production ML models
Required skills
Static Timing Analysis (STA), timing closure, ECO implementation, crosstalk and noise analysis, RTL to Netlist flow, deep sub-micron process modeling, DFT timing closure, methodology and flow development
Preferred skills
Experience with GPUs, CPUs, DPUs, or SoCs; automation in timing flows
Technologies
Industry-standard STA tools, timing constraints management tools
Responsibilities
Drive timing analysis and closure at block, cluster, and full chip levels; collaborate with Physical Design and DFX teams to develop timing closure strategies; enhance timing convergence flows; contribute to DFT logic understanding and timing closure; work on timing closure of digital logic/macros in AMS designs/IPs
Seniority
Mid-Senior level (5+ years BS or 2+ years MS)
