Static Timing Analysis (STA) Engineer
Core
Execute static timing analysis and support timing closure for advanced FPGA designs to ensure high-performance, power-efficient outcomes.
Role type
Static Timing Analysis (STA) Engineer
Builds
FPGA designs
Domain
Semiconductor / FPGA Design
Required skills
Static Timing Analysis (STA) fundamentals, setup/hold analysis, timing path analysis, clocking analysis, CDC basics, industry-standard STA tools (e.g., PrimeTime), synthesis and place & route flows, RTL design (Verilog/SystemVerilog), FPGA or ASIC design methodologies, root cause analysis, timing report interpretation
Preferred skills
FPGA architecture knowledge, advanced process node experience, high-speed design experience, scripting (Tcl/Python) for automation, large-scale engineering environment experience
Technologies
PrimeTime, Verilog, SystemVerilog, Tcl, Python
Responsibilities
Perform static timing analysis including setup/hold checks and constraint validation, identify and debug timing violations, develop and validate timing constraints, collaborate with cross-functional teams for timing convergence, apply STA methodologies and contribute to flow automation, support performance/power/area optimization
Seniority
Senior, hands-on IC
