Senior/Principal Physical Design Engineer
Core
End-to-end implementation of complex IC physical designs from synthesis to sign-off to increase clock speed for AI inference systems.
Role type
Senior/Principal Physical Design Engineer
Builds
Next-generation ASIC/SoC chips for AI accelerators and high-performance computing
Domain
Semiconductor hardware design, AI infrastructure, advanced process nodes (7nm, 5nm)
Deliverable
production ML models
Required skills
ASIC/SoC physical implementation, floorplanning, placement, clock tree synthesis (CTS), routing, sign-off, synthesis, static timing analysis (STA), power planning, IR drop analysis, DFT integration, EDA tool proficiency, scripting (TCL/Perl/Python), CMOS technology understanding, timing closure, signal integrity
Preferred skills
Low-power design methodologies, multi-power domain architectures, formal verification, high-performance computing (HPC) experience, AI accelerator design, networking chip experience, leveraging advanced AI tools in engineering workflows
Technologies
Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre
Responsibilities
Drive physical implementation of ASIC/SoC designs including floorplanning, placement, CTS, routing, and sign-off; Work on synthesis, timing analysis, and optimisation to achieve best PPA metrics; Perform power planning and analysis addressing IR drop and electromigration; Ensure DRC, LVS, and physical verification compliance; Collaborate with DFT engineers to integrate design-for-test structures; Develop flows in EDA tools; Interface with foundries and process engineers; Work with RTL and architecture teams to drive design feasibility
Seniority
Senior/Principal, hands-on IC