ASIC Principal Design Engineer
Core
Architecting high-performance blocks and defining micro-architecture for advanced networking ASICs to deliver maximum throughput and minimum power.
Role type
Principal ASIC Design Engineer
Builds
Next-generation networking ASICs for the intelligent edge
Domain
Networking hardware / VLSI design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Verilog RTL coding, ASIC architecture, logic design, timing constraint analysis, high-speed serial interfaces, multi-domain clock synchronization, ASIC debugging
Preferred skills
Synopsys Design Compiler, Verplex LEC, Spyglass, Ethernet/FCoE protocols, high-performance memory subsystems
Technologies
Verilog, Synopsys Design Compiler, Verplex LEC, Spyglass
Responsibilities
Define and architect high-performance blocks for networking ASICs; Perform micro-architecture and logic design; Collaborate with verification teams on test plans and debugging; Collaborate with physical design teams on timing constraints and fixes
Seniority
Principal, technical leadership & complex problem solving
