Staff Engineer, Digital Design Engineering
Core
Lead the development, curation, and delivery of reusable strategic digital IPs (accelerators, datapath, high-speed interfaces) to accelerate product development across business units.
Role type
Staff Digital Design Engineer (IP Architecture & Delivery)
Builds
Reusable digital IP blocks, IP catalogs, and design management infrastructure for ASIC/SoC products.
Domain
Semiconductor / Digital Design / IP Development
Deliverable
production ML models | product features | infrastructure
Required skills
Verilog/SystemVerilog RTL coding, digital block architecture (accelerators, datapath), heterogeneous processor subsystems (RISC-V, ARM, DSP), high-speed interface protocols (PCIe, DDR, MIPI, Ethernet), ASIC/SoC development lifecycle, timing closure, CDC, DFT, DV planning, IP evaluation and benchmarking, design review leadership.
Preferred skills
AI tool adoption for design efficiency, cross-functional stakeholder management, ambiguity resolution.
Technologies
Verilog, SystemVerilog, Methodics, Perforce, GitHub, CoreSight, GIC, DMA, MMU, SPU, TZC, APB/AHB/AXI.
Responsibilities
Architect and design key digital blocks with PPA optimization; mentor digital design engineers on CDC, synthesis, and timing; evaluate and integrate third-party IPs; manage IP catalog and design flows; drive adoption of AI tools; conduct design reviews and enforce quality metrics.
Seniority
Staff, technical leadership & hands-on IC
