SoC PnP Architect
Core
Architecting and optimizing system-on-chip (SoC) performance, power, and efficiency across complex silicon platforms from pre-silicon modeling to post-silicon characterization.
Role type
Senior IC SoC Performance and Power (PnP) Architect
Builds
High-performance silicon platforms optimized for compute, interconnect, memory, and I/O subsystems
Domain
Semiconductor / Computer Architecture / System-on-Chip Design
Deliverable
production ML models | product features | infrastructure
Required skills
SoC performance architecture, pre-silicon performance analysis, simulation and hardware emulation (Palladium, Veloce, ZeBu), cycle-accurate and transaction-level modeling, waveform-based debug, latency/bandwidth/throughput characterization, CHI/AXI/PCIe/CXL protocol debug, SystemC/TLM modeling, model-to-silicon correlation, post-silicon performance characterization, root-cause analysis of power gaps, coherent interconnect fabrics, DDR memory subsystems, DVFS and power management, Linux and bare-metal debugging, kernel-level profiling (perf, ftrace), C/C++ and Python for tool development
Preferred skills
Experience with accelerator performance (CPU/GPU/NPU/DSP), workload characterization, architectural tradeoff analysis, cross-functional leadership in architecture decisions
Technologies
Palladium, Veloce, ZeBu, SystemC, TLM, Linux, C, C++, Python, perf, ftrace, CHI, AXI, PCIe, CXL, DDR, PMU
Responsibilities
Drive system-level performance, power, and efficiency investigations; develop and calibrate performance/power models; correlate pre-silicon projections with silicon measurements; debug performance bottlenecks across compute, memory, and I/O; tune system performance under power/thermal constraints; build automation frameworks for telemetry and analysis; present architectural recommendations to leadership
Seniority
Senior, hands-on IC