Lead Physical Design Engineer
Core
End-to-end implementation of complex IC physical designs (ASIC/SoC) from synthesis to sign-off, optimizing performance, power, and area for advanced AI chips.
Role type
Lead Physical Design Engineer (IC/SoC)
Builds
Next-generation AI accelerator chips and silicon systems
Domain
Semiconductor hardware design, AI accelerators, advanced process nodes (7nm, 5nm)
Deliverable
production ML models | product features
Required skills
Full-chip physical design (floorplanning, placement, CTS, routing, sign-off), timing analysis (STA), power planning and IR drop analysis, DRC/LVS verification, EDA tool expertise (Cadence Innovus, Synopsys Fusion Compiler, Calibre), scripting (TCL, Perl, Python), CMOS technology and semiconductor physics knowledge, team leadership and mentorship
Preferred skills
Experience with high-performance computing (HPC) or networking chips, leveraging advanced AI tools for engineering workflows
Technologies
Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, TCL, Perl, Python
Responsibilities
Drive physical implementation of ASIC/SoC designs including floorplanning, placement, clock tree synthesis, routing, and sign-off; Lead or contribute to full-chip execution and block ownership; Optimize performance, power, and area (PPA) metrics; Ensure design rule check (DRC) and layout vs. schematic (LVS) compliance; Collaborate with DFT engineers to integrate design-for-test structures; Mentor junior engineers and build physical design practices
Seniority
Senior, hands-on IC with leadership responsibilities