Principal NoC IP Micro-Architect
Core
Designing logic, RTL coding, and simulation for Network on Chip (NoC) IPs and FPGA subsystems for full chip integration.
Role type
Principal NoC IP Micro-Architect
Builds
Network on Chip IPs and FPGA subsystems
Domain
Semiconductor / Hardware Design
Deliverable
production ML models | product features | infrastructure
Required skills
System Verilog, VCS/Synopsys simulators, Lint, Synthesis, C/C++/Perl/Python/TCL/Unix Shell scripting, FPGA design, RTL validation, NoC IP development, AI in development process
Preferred skills
FPGA design, RTL validation, AI in development process
Technologies
System Verilog, VCS, Synopsys, Lint, C, C++, Perl, Python, TCL, Unix Shell
Responsibilities
Develop logic design, RTL coding, and simulation for NoC IPs; define architecture and microarchitecture features; create prototypes and specify system requirements; design logic diagrams and codes for implementation; deliver software models for device bring-up; apply RTL implementation techniques to meet power, performance, and area goals; review verification plans and resolve failing RTL tests; mentor technical members and guide the NoC team.
Seniority
Principal, hands-on IC with mentorship
