ASIC Design Engineer
Core
Define and architect high-performance blocks for advanced networking ASICs, performing micro-architecture and logic design to maximize throughput while minimizing power.
Role type
Senior IC ASIC Design Engineer (Networking)
Builds
High-performance networking ASICs
Domain
Networking hardware / VLSI
Deliverable
production ML models | product features
Required skills
Verilog RTL coding, ASIC design for networking protocols, high-speed serial interfaces, multi-domain clock synchronization, timing constraint analysis, ASIC debugging
Preferred skills
Synopsys Design Compiler, Verplex LEC, Spyglass, high performance memory subsystems
Technologies
Verilog, Synopsys Design Compiler, Verplex LEC, Spyglass
Responsibilities
Define and architect high-performance blocks for the latest, most advanced networking ASICs; Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power; Collaborate with the verification team in the development of the testplan and assist in debugging test failures; Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
Seniority
Senior, hands-on IC
