Digital Senior Design Engineer
Core
Design power and area optimized functional blocks for Ciena's Wavelogic optical fiber transmission products.
Role type
Senior Digital Design Engineer
Builds
High-speed connectivity optical transmission solutions
Domain
Telecommunications / Optical Fiber
Deliverable
production ML models | product features
Required skills
System Verilog, digital design synthesis, static timing analysis (STA), timing closure, asynchronous clock crossing, RTL design, design assertions, timing constraints, synthesis log analysis, timing report analysis
Preferred skills
digital silicon design backend process, low power design, OTN/FlexO/B100G protocols, Ethernet (100GE+), Git, Jira, Python, Make, bash
Technologies
System Verilog, Python, Git, Jira
Responsibilities
Read and understand architecture and functional requirements specifications; produce and review implementation specification documents; create and integrate RTL code, algorithms, and functions; test and debug code during simulation and regression verification; assist verification team in determining coverage and provide design assertions; craft timing constraints and participate in synthesis log, constraint, and timing report reviews; assist in lab validation of product prototypes; report status updates regularly
Seniority
Senior, hands-on IC