Physical Design Engineer II (PNR/Physical Verification/STA/EMIR)
Core
Physical Design Engineer responsible for implementation, timing closure, and signoff in advanced technology nodes.
Role type
Senior IC physical design engineer (PNR/STA/Verification)
Builds
Next-generation PHY IP and digital designs for tapeout
Domain
Semiconductor / VLSI Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
floor planning, power grid design, place and route, clock tree synthesis, timing closure, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure, scripting languages, static timing analysis, DRC/DFM/LVS/ANT/ERC violation fixing
Preferred skills
experience in N7/N5 and below technology nodes
Technologies
N7, N5, DRC, LVS, Antenna, EM/IR, DFM, STA
Responsibilities
Lead next-generation physical design methodology and flow development; Perform physical design implementation including floor planning, power grid design, place and route, clock tree synthesis, timing closure, and signoff; Fix physical design violations including DRC, DFM, LVS, ANT, and ERC; Collaborate with RTL and Analog teams to ensure successful tapeouts.
Seniority
Mid-level, hands-on IC