Debug/Trace/Profiling Design Engineer
Core
Designing industry-leading debug, trace, and profiling IP for RISC-V processor cores to enable high-performance SOC designs across AI, automotive, and data center markets.
Role type
Senior IC hardware design engineer (debug/trace/profiling IP)
Builds
Customizable RISC-V processor subsystem IP including Essential, Intelligence, Performance, and Automotive product lines
Domain
Semiconductor / Chip Design / RISC-V Architecture
Deliverable
production ML models | product features | infrastructure
Required skills
Debug/trace/profiling architecture, JTAG/cJTAG interfaces, CPU architecture, SoC design, RTL design (Verilog/System Verilog/VHDL), Chisel/Scala, Object-oriented and/or functional programming
Preferred skills
RISC-V International Association engagement, Git/Jira/Confluence, documentation creation
Technologies
Chisel, Scala, FIRRTL, TileLink, RISC-V, JTAG, cJTAG, Verilog, System Verilog, VHDL
Responsibilities
Architect, design, and implement debug, trace, and profiling hardware; Implement RTL generators for configurable design-in; Integrate design content into Chisel/FIRRTL framework; Perform initial sandbox verification and collaborate on verification test plans
Seniority
Senior, hands-on IC
