Micro-Architect and RTL Designer
Core
Designing high-performance silicon micro-architecture and RTL for compute, memory management, and high-speed connectivity blocks to support AGI workloads.
Role type
Senior IC silicon micro-architect and RTL designer
Builds
ASICs and SOCs for high-performance compute, memory management, and high-speed connectivity
Domain
Semiconductor hardware design for AGI/GenAI
Deliverable
production ML models | product features
Required skills
SystemVerilog, Python, C/C++, micro-architecture design, RTL design, design synthesis, design lint, verification flow, emulation platforms, high-speed I/O IP, data movement logic (caches, buffers, crossbars)
Preferred skills
verification methodologies, high-speed I/O IP, data movement logic
Technologies
SystemVerilog, Python, C/C++, emulation platforms
Responsibilities
Contribute to silicon architecture-to-design methodology across blocks and full-chip; Own subsystem or chip-level design deliverables from micro-architecture to sign-off; Plan and drive micro-architecture reviews and timing closure; Collaborate with verification and physical design teams for performance-power-area optimization
Seniority
Senior, hands-on IC
