Sr Principal Engineer AI/ML
Core
Designing and leading the RTL development of an AI-enabled RISC-V CPU core, including vector extensions and matrix engines for physical AI applications.
Role type
Senior IC CPU IP Design Engineer
Builds
RISC-V CPU cores with AI capabilities (vector and matrix engines) for semiconductor foundry clients
Domain
Semiconductor / CPU Architecture / RISC-V
Deliverable
production ML models | product features
Required skills
Microprocessor architecture, RISC-V instruction set, System Verilog/Verilog/VHDL, CPU pipeline design, Cache coherency, Logic design principles, Timing and power analysis, RTL design configuration, Functional verification strategy
Preferred skills
RISC-V/ARM/MIPS CPU design, Hardware multi-threading, Virtualization, SIMD designs, Vector/matrix-enabled CPU design, Low-power microarchitecture, SoC integration, Safety and Security microarchitecture, Scripting (Perl/Python)
Technologies
System Verilog, Verilog, VHDL, RISC-V, Perl, Python
Responsibilities
Drive micro-architecture and design of critical CPU core blocks; Design RISC-V Vector CPU core and custom extensions; Design AI-enabled Matrix engine; Explore high-performance strategies with modeling team; Perform microarchitecture development from exploration to detailed specification; Configure RTL design for PPA (Power, Performance, Area) goals; Assist in RTL design verification and performance validation; Partner on physical design aspects (timing, area, reliability, testability, power)
Seniority
Senior, hands-on IC
