Principal Digital Design Engineer
Core
Lead digital design architecture, RTL implementation, and low-power design for power management ICs serving consumer, industrial, and automotive applications.
Role type
Principal Digital Design Engineer (Power Management ICs)
Builds
Power management chips including DC-DC PMIC/POL, multiphase controllers, LED drivers, and SiC drivers
Domain
Semiconductor / Power Electronics
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital RTL design, ASIC synthesis, timing analysis, CDC, P&R, UPF, System Verilog, Verilog, TCL, Perl, Python, XML, Power converter topologies, Digital architecture trade-offs
Preferred skills
Experience with SOCV, Emulation, FPGA, Post-silicon validation, MCU systems, Digital control peripherals
Technologies
Verilog, TCL, Perl, Python, XML, SOCV, Emulation, FPGA, UPF
Responsibilities
Lead digital design architecture and RTL teams, execute tool flows for IP quality control, drive architecture to micro-architecture to RTL implementation, support bring-up on pre-silicon platforms, own technical outcome of design and verification, identify and implement new systems/tools, support post-silicon validation
Seniority
Principal, hands-on IC design and team leadership