Senior CPU Power Delivery Engineer
Core
Design and analyze power delivery networks (PDN) for high-performance CPU clusters across advanced process nodes.
Role type
Senior CPU Power Delivery Engineer
Builds
High-performance mobile and compute SoCs
Domain
Semiconductor, CPU subsystems, power integrity
Deliverable
production ML models | product features | infrastructure
Required skills
PDN design and analysis, impedance modeling, frequency-domain and time-domain simulation, power grid architecture definition, IR drop analysis, dynamic voltage droop analysis, silicon characterization, PMIC/VR selection
Technologies
Apache Redhawk, Voltus
Responsibilities
Design and analyze power delivery networks (PDN) for CPU clusters across advanced process nodes; Develop PDN impedance models and perform frequency-domain and time-domain simulations; Define power grid architecture, decap strategy, and bump/pin assignment; Perform IR drop and dynamic voltage droop analysis; Work with microarchitecture and physical design teams to optimize power gating and DVFS; Characterize silicon power behavior during bring-up; Define power delivery specifications for package, board, and PMIC/VR selection.
Seniority
Senior, hands-on IC
