Lead Design Engineer
Core
Lead physical design implementation for state-of-the-art interface IPs (DDR, PCIe, etc.) and test chips at advanced process nodes (7nm/5nm/3nm/2nm), optimizing for performance, power, and area.
Role type
Senior IC physical design engineer (backend)
Builds
Production ASIC IPs and SoCs for semiconductor foundries
Domain
Semiconductor / VLSI / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
hierarchical physical design strategies, static timing analysis, low power design, EM/IR/crosstalk analysis, formal verification, physical verification (DRC/LVS/Antenna), DFM, DFT, ASIC design flow, deep sub-micron technology issues
Preferred skills
Cadence EDA tools (Genus, Innovus, Tempus, Voltus), automation scripting (Makefile/Tcl/Tk/Perl/python), AI integration
Technologies
Genus, Innovus, Tempus, Voltus, Quantus, PVS, Tcl, Perl, Python, Makefile
Responsibilities
Floor planning, power grid design, place and route, clock tree synthesis, timing/SI closure, power/EM-IR signoff, physical verification, DFM closure, PPA optimization of interface IPs, collaboration with RTL and Analog teams for tapeout
Seniority
Senior, hands-on IC
