Staff/Senior Staff Physical Design Engineer (Technical Lead)
Core
Lead physical design for next-generation in-memory computing silicon products, optimizing PPA for edge-to-cloud applications.
Role type
Staff/Senior Staff Physical Design Engineer (Technical Lead)
Builds
High-performance in-memory computing chips for edge-to-cloud computing
Domain
Semiconductor design / AI hardware
Deliverable
production ML models
Required skills
Physical Design (PD), Static Timing Analysis (STA), PPA optimization, Tcl scripting, Python scripting, Floorplanning, Clock tree synthesis (CTS), Sign-off verification
Preferred skills
SOC clocking, FEV/VCLP specialized skills, Advanced nodes (7nm, 5nm)
Technologies
Cadence Innovus, Cadence Tempus, Voltus, Apache, Pegasus, Calibre
Responsibilities
Lead a small team of PD engineers providing technical direction and architectural oversight; Take personal hands-on ownership of critical high-congestion or timing-critical blocks; Act as primary architect for PD convergence and implement custom PPA recipes; Develop sophisticated Tcl and Python scripts for flow automation and sign-off verification; Manage stakeholders with RTL, DFT, and Synthesis teams to ensure schedule adherence; Ensure sub-chip meets gold-standard sign-off criteria including STA, EM/IR, and Physical Verification.
Seniority
Senior Staff, hands-on IC with mentorship