Sr. Staff Physical Design PPA Engineer
Core
Developing and innovating design recipes to improve Power/Performance/Area (PPA) for Physical Design execution on premium IPs for high-performance computing devices.
Role type
Sr Staff Physical Design PPA Engineer
Builds
Premium IPs for mobile, automotive, and custom market segments
Domain
Semiconductor / ASIC / Physical Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical Design Implementation, Synthesis, Floor Planning, Place & Route, Timing Signoff, Power Grid Optimization, Area/Congestion Optimization, Scripting (TCL/Perl/Shell/Python), SOC/ASIC Design Flow, Taping Out
Preferred skills
7nm Finfet or smaller process nodes, Clock Tree Synthesis (CTS), Reliability/Signal Integrity/Noise Closure, DFM Closure
Technologies
Industry P&R/STA flows and tools
Responsibilities
Lead PPA initiatives by identifying opportunities and executing solutions; Drive flow and methodology improvements for automation; Perform hands-on synthesis, floor planning, place & route, and signoff flows; Interact with RTL counterparts and SOC teams to resolve design issues and optimize flows.
Seniority
Sr Staff, hands-on IC with strategic initiative ownership