EDA Tools Hardware Engineer
Core
Develop and maintain full-chip physical implementation flows, including floor planning, hierarchical block integration, placement, routing, power grid planning, and clock tree synthesis to enable scalable SoC assembly.
Role type
Senior IC physical design flow engineer
Builds
Full-chip physical implementation flows and scalable SoC assembly methodologies
Domain
Semiconductor manufacturing / Physical Design / EDA
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical design fundamentals (placement, routing), Clock tree synthesis (CTS), Full-chip integration methodologies, Innovus, Linux scripting and automation
Preferred skills
Static timing analysis (STA), Power grid design and IR drop concepts, Large SoC or multi-block design implementation flows
Technologies
Innovus, Linux
Responsibilities
Develop floor planning and partitioning strategies; Execute hierarchical block integration; Coordinate chip-level placement and routing; Perform power grid planning and analysis; Integrate clock tree synthesis (CTS) strategies; Define methodology for hierarchical design reuse and integration
Seniority
Senior, hands-on IC
