Micro-architect/Logic Designer, Coherent Interconnect
Core
Leading micro-architecture development of custom coherent interconnect IP and last level cache blocks for high-performance computing devices.
Role type
Senior IC micro-architect/logic designer (coherent interconnect)
Builds
Custom coherent interconnect IP and last level cache (LLC) blocks
Domain
Semiconductor / High-performance computing / System-on-Chip (SoC)
Deliverable
production ML models | product features
Required skills
RTL design, Verilog, ASIC design flow, microarchitecture development, timing closure, performance/power optimization, cache design, directory snoop filter protocols, on-chip network topologies, AMBA/ACE/AXI/CHI protocols
Preferred skills
Scripting (Perl/Python), STA, DFT, ECO flows, memory controller design
Technologies
Verilog, AMBA5 CHI, AMBA4 ACE, AXI, Perl, Python
Responsibilities
Drive development of custom coherent interconnect IP and LLC blocks; Define next-generation interconnects with architects; Perform microarchitecture development and specification; Verify functionality with verification team; Collaborate with implementation for timing and area; Produce quality RTL meeting PPA goals; Mentor junior engineers
Seniority
Senior, hands-on IC
