Senior ASIC Physical Design Engineering Technical Lead
Core
Senior ASIC Physical Design Technical Lead responsible for RTL-to-GDSII implementation, timing closure, and power integrity for AI-era hardware platforms.
Role type
Senior IC ASIC Physical Design Technical Lead
Builds
Cisco core Switching, Routing, and Wireless silicon products
Domain
Semiconductor / ASIC Design / AI Infrastructure
Deliverable
production ML models
Required skills
RTL-to-GDSII flow, Logic Synthesis, Hierarchical Floorplanning, Place and Route, Static Timing Analysis, Power Integrity, Equivalence checks, Clock Tree Synthesis, ECO implementation, EDA tools (Innovus, Primetime/Tempus, Redhawk/Voltus, Calibre), Python/TCL/Perl scripting
Preferred skills
Hierarchical design, physical convergence, custom clock (H-Tree/Mesh), timing constraints definition, automation scripting
Technologies
Innovus, Primetime, Tempus, Redhawk, Voltus, Calibre, 7nm/5nm/3nm processes
Responsibilities
Execute STA setup and sign-off across multi-mode/multi-corner scenarios; Guide CTS strategies; Analyze tool flows for efficiency; Complete Functional and Timing ECO implementation; Collaborate with RTL, DFT, and EDA vendor teams
Seniority
Senior, hands-on IC with technical leadership
