Engineer - Physical design
Core
Physical design engineer specializing in RTL-to-GDSII flow for next-generation SoC projects, focusing on synthesis, placement, CTS, routing, and timing closure.
Role type
Junior IC physical design engineer (SoC)
Builds
SoC implementations
Domain
Semiconductor / VLSI / ASIC
Required skills
RTL-to-GDSII flow, Static timing analysis, Python scripting, Tcl scripting, PrimeTime, Fusion Compiler/Genus/Innovus, Verilog, Linux environment
Preferred skills
Advanced-node implementation, Low-power concepts (UPF), Signal integrity, EM/IR analysis, DFT flows, AI coding assistants
Technologies
Synopsys PrimeTime, Fusion Compiler, Genus, Innovus, Python, Tcl, Linux
Responsibilities
Complete RTL synthesis, floorplanning, placement, CTS, routing, and GDSII generation; Analyze and improve PPA; Conduct static timing analysis and troubleshoot violations; Review timing constraints and tool reports; Assist with physical verification (DRC, LVS, SI, EM/IR); Develop automation scripts; Use AI tools for scripting and debugging.
Seniority
Junior, hands-on IC