Lead Product Engineer
Core
Lead timing signoff and ECO for advanced System-on-Chips (SoCs) using industry-standard tools, driving timing closure and supporting technology node bring-up.
Role type
Senior IC physical design engineer (timing closure)
Builds
Advanced-node SoCs (5nm, 3nm, 2nm) and timing signoff flows
Domain
Semiconductor / Electronic Design Automation (EDA)
Required skills
Static Timing Analysis (STA), PrimeTime, Tempus/Certus, MMMC scenarios, OCV/AOCV/SOCV, LVF, PBA/GBA, timing ECOs, PPA optimization, Tcl/Python scripting
Preferred skills
SPICE simulation and correlation, debugging large SoC environments, AI/LLM concepts, CLI-based infrastructure automation, agent-based solutions
Technologies
PrimeTime, Tempus, Certus, Python, Tcl
Responsibilities
Perform static timing analysis across MMMC scenarios; Debug setup/hold violations, SI, and variation-related issues; Drive timing closure using PBA/GBA and advanced derating techniques; Implement physical-aware timing ECOs and optimize PPA; Perform STA vs SPICE correlation and improve signoff accuracy; Support foundry enablement and technology node bring-up (5nm, 3nm, 2nm); Develop automation using Tcl/Python for timing workflows
Seniority
Senior, hands-on IC
