Staff Engineer - DFT
Core
Design, implement, and verify Digital Design for Test (DFT) and Static Timing Analysis (STA) flows for networking SoCs spanning copper and optical products.
Role type
Staff Engineer - DFT/STA
Builds
DFT architecture, testability strategies, timing constraints, and test flows for SoC tapeout.
Domain
Semiconductor / Networking / Digital IC Design
Required skills
SCAN/ATPG/JTAG/MBIST, Chip-level STA flows, Gate-level simulation (DTT modes), Test structure design, Scan insertion, Test mode timing constraints, Cross-domain DFT resolution, Industry standard DFT tools (Synopsys/Mentor), JTAG (IEEE1149.1/6), Post-Si ATE debug, Memory BIST generation, Perl/Tcl scripting
Technologies
Synopsys, Mentor, Perl, Tcl
Responsibilities
Develop timing constraints and technology library infrastructure, define and implement DFT/STA flows, perform DFT/STA verification and post-Si bring-up, collaborate with Logic/Physical design/STA/ATE teams, resolve cross-domain DFT issues, generate and verify Memory BIST.
Seniority
Staff, hands-on IC
