Physical Design Lead
Core
Lead end-to-end physical implementation of complex SoCs and IPs on advanced technology nodes, owning large design partitions or top-level activities including floorplanning, place-and-route, timing closure, and signoff.
Role type
Senior IC Physical Design Lead
Builds
Complex SoCs and IP blocks for semiconductor products
Domain
Semiconductor / VLSI Physical Design
Required skills
SoC physical design, floorplanning, place-and-route, timing closure, static timing analysis (STA), multi-corner multi-mode (MCMM) optimization, physical verification, DRC/LVS, Tcl scripting, low-power design methodologies, EDA tool expertise, cross-functional collaboration
Preferred skills
Leading physical implementation for large-scale SoCs across multiple sites, developing organization-wide design methodologies, variation-aware timing closure, AI-assisted design optimization
Technologies
Cadence Innovus, Synopsys Fusion Compiler, ICC2, PrimeTime, Ansys RedHawk, UPF/CPF
Responsibilities
Lead RTL-to-GDSII implementation flow, drive PPA targets, develop automation frameworks, mentor engineers, perform signoff closure, collaborate with architecture and verification teams
Seniority
Senior, hands-on IC
