Physical Design Engineer, New Grad
Core
Run and improve RTL to GDS flow on advanced process nodes for RDU chip designs.
Role type
New grad physical design engineer (IC)
Builds
RDU chips (Reconfigurable Dataflow Units) for AI inference platforms
Domain
Semiconductor / VLSI / AI Infrastructure
Deliverable
production ML models
Required skills
RTL to GDS flow, synthesis, place and route, TCL scripting, Python scripting, VLSI/digital IC design
Preferred skills
Static timing analysis, physical design rules on advanced nodes, AI tools usage, tape-out experience
Technologies
Cadence Genus, Cadence Innovus, Cadence Cerebrus, TSMC
Responsibilities
Run synthesis and place and route using Cadence tools, Write scripts to automate physical design flow, Debug timing and congestion issues, Work with tool vendors on bugs
Seniority
Junior, New Grad
