PRINCIPAL ENGINEER, ASIC DESIGN
Core
Drive IP, Subsystem, and SoC development for next-generation memory and storage products, owning design from micro-architecture through RTL compose, integration, and physical hardware assistance.
Role type
Principal IC ASIC Design Engineer (SoC)
Builds
Reusable IP blocks, subsystems, and System-on-Chip (SoC) designs for memory and storage solutions
Domain
Semiconductor / Memory and Storage / Digital Design
Required skills
Micro-architecture, RTL design (Verilog/System Verilog), SoC integration, CDC methodologies, Synthesis/STA, Power analysis, Scripting
Preferred skills
LPDDR Subsystem design, CPU Subsystems, SoC Test Controller, ASIC controllers for storage/memory, Post-silicon debug
Technologies
Verilog, System Verilog, Lint, CDC, Synthesis, STA, Power analysis tools
Responsibilities
Own end-to-end IP and SoC development from micro-architecture to RTL integration; Drive SoC integration including CDC, lint, synthesis, STA, and power analysis; Define and review module interfaces and system-level architecture; Collaborate with Architecture, Verification, FW, DFT, Synthesis, and Physical Design teams; Support post-silicon debug and bring-up activities; Provide technical mentorship and participate in design reviews
Seniority
Principal, hands-on IC design with mentorship
