Senior Staff Engineer Design
Core
Develop next-generation semiconductor products by driving the complete RTL design cycle from specification to micro-architecture and implementation, optimizing for Power, Performance, and Area (PPA).
Role type
Senior Staff RTL Design Engineer
Builds
SoC/IP blocks for power systems and IoT
Domain
Semiconductor / VLSI
Required skills
RTL design, Verilog, SystemVerilog, micro-architecture, PPA optimization, Lint, CDC, Synthesis, CLP, UPF, AMBA protocols (AHB, AXI), low-power design, debugging
Preferred skills
Mentorship, cross-functional collaboration
Technologies
Verilog, SystemVerilog, UPF, AMBA, AHB, AXI
Responsibilities
Own the RTL design cycle from specification analysis to micro-architecture definition and RTL implementation; Develop detailed micro-architecture documents from high-level product specifications; Translate architecture and design requirements into high-quality RTL; Collaborate with architecture teams to review and refine design and micro-architecture proposals; Deliver RTL that is functionally correct and optimized for Power, Performance, and Area (PPA); Drive RTL quality sign-off activities including Lint, CDC, Synthesis, and CLP checks; Implement and review low-power design methodologies using UPF and related power-intent constructs; Work closely with verification, physical design, and integration teams to resolve design issues; Debug and root-cause functional, synthesis, timing, and low-power challenges; Ensure compliance with coding standards and design best practices throughout the development cycle; Support design reviews and provide technical mentorship to junior engineers when required.
