ASIC Engineer
Core
Define, design, and take end-to-end Front-End ownership of ASIC subsystems for high-performance silicon deployed in Cisco platforms.
Role type
Senior IC ASIC Design Engineer
Builds
High-performance ASICs for hyperscale infrastructure, data centers, and service provider networks
Domain
Semiconductor / ASIC Design
Required skills
ASIC design, RTL coding (Verilog/SystemVerilog), timing closure, power optimization, clock gating, simulation, synthesis, static timing analysis
Preferred skills
Cross-functional collaboration, technical documentation, problem-solving, system architecture influence
Technologies
Verilog, SystemVerilog, 2.5D fanout technologies
Responsibilities
Design and implement high-frequency, high-performance RTL; Lead design specifications and technical reviews; Drive technical execution across architecture, design, verification, and physical implementation; Mentor engineers; Lead debug and root-cause analysis; Influence system architecture and key design decisions
Seniority
Senior, hands-on IC
