Lead FPGA Timing & Characterization Silicon Design Engineer
Core
Lead the development, validation, silicon correlation, and release of FPGA timing models to enable industry-leading FPGA implementation and timing analysis tools.
Role type
Senior Member of Technical Staff (SMTS), Lead FPGA Timing & Characterization Engineer
Builds
Production-quality FPGA timing libraries and characterization flows
Domain
Semiconductor / FPGA Design / Digital Logic
Required skills
FPGA architecture, Static Timing Analysis (STA), PVT variation, OCV/POCV methodologies, silicon characterization, root-cause analysis, flow automation, statistical timing techniques, cross-functional leadership
Preferred skills
Large-scale flow automation, data analytics, Vivado/Quartus tools, mentoring
Technologies
Python, Perl, Tcl, Vivado, Quartus
Responsibilities
Establish validation frameworks for FPGA timing library quality, drive root-cause analysis for timing discrepancies, develop regression suites and DRC checks, drive characterization of FPGA resources, develop automation flows, own planning and execution of Timing Library releases, perform QoR analysis, coordinate release readiness reviews, provide technical status updates
Seniority
Senior, hands-on IC with mentorship responsibilities
