CareerPlan

Senior Physical Design Methodology Engineer, PPA Improvement Technology Scaling

US, CA, Santa ClaraFull-time$168k2026-10-28 → 2026-11-10

Core

Developing physical design methodologies and automation for graphics processors and SOCs to solve state-of-the-art physical design problems.

Role type

Senior Physical Design Methodology Engineer (PPA Improvement Technology Scaling)

Builds

Graphics processors and System-on-Chips (SOCs)

Domain

Semiconductor / Chip Design

Required skills

Physical Design Engineering, Floor planning, Clock and Power distribution, Place and Route, Integration and Verification, Hierarchical design approach, Timing and physical convergence, Design for Yield and Manufacturability, EM and IR closure, Thermal management, EDA tools, Programming and scripting (Perl, Python, C++)

Preferred skills

Physical Design related to CPU designs

Technologies

EDA tools, Perl, Python, C++