RTL Design Engineer - PCIE, Ethernet, USB and DDR
Core
Develop and maintain RTL design and integration for in-house/vendor IPs, subsystems, and SoCs, focusing on PCIE, Ethernet, USB, and DDR protocols.
Role type
Senior RTL Design Engineer (SoC/Protocol)
Builds
High-performance SoCs and subsystems for AMD processors
Domain
Semiconductor / VLSI / Digital Design
Required skills
RTL coding, PCIE, Ethernet, USB, DDR, AMBA, VLSI fundamentals, FIFO, arbitration techniques, static QC (LINT, CDC, RDC, CLP/VCLP), timing closure, constraint development (SDC, UPF)
Preferred skills
IPXACT, QC tools/flows
Technologies
PCIE, Ethernet, USB, DDR, AMBA, SDC, UPF, LINT, CDC, RDC, CLP/VCLP, IPXACT
Responsibilities
Develop and maintain design and integration for various in-house/vendor IPs, subsystems and SoC; Ensure quality of the IP/Subsystem/SoC through various static QCs; Develop/Own various constraints like SDC, UPF; Interact with various stakeholders to ensure timing closure and verification robustness
Seniority
Senior, hands-on IC
