ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr)
Core
Designing system power management IP cores and subsystems for Snapdragon SoCs used in mobile, compute, IoT, and automotive markets.
Role type
Senior ASIC RTL Design Engineer
Builds
System power management IP cores and subsystems for Snapdragon SoCs
Domain
Semiconductor / Hardware Design
Required skills
Verilog/SystemVerilog, RTL design, Micro-architecture, Synthesis, LEC, Netlist CLP, UPF, Clock domain crossing, Bus protocols (AHB, AXI, SPMI, I2C, SPI), Perl/TCL/Python, Static tool checks (Lint, CDC, CLP), Database management (Clearcase/Clearquest)
Preferred skills
Post-Si debug, Formal verification with Cadence LEC, Low power design methodology
Technologies
Verilog, SystemVerilog, UPF, Cadence LEC, Spyglass, Clearcase, Clearquest, Perl, TCL, Python
Responsibilities
Micro-architecture and RTL design for IP Cores/subsystems, Coordinate with Systems/Verification/SoC/SW/PD/DFT teams, Enable SW teams to use HW blocks, Qualify designs using static tool checks, Perform Synthesis, LEC, and Netlist CLP
Seniority
Senior, hands-on IC
