Synthesis & STA Engineer – High-Speed SerDes
Core
Drive logic synthesis and static timing analysis (STA) for digital controller and DSP blocks within high-speed analog/mixed-signal SerDes PHY designs.
Role type
Senior IC digital synthesis and STA engineer (high-speed SerDes)
Builds
High-speed SerDes and connectivity ASICs for cloud service providers, servers, and network OEMs
Domain
Semiconductor design, high-speed analog/mixed-signal SerDes, advanced process nodes (5nm/3nm)
Required skills
RTL synthesis, static timing analysis (STA), SDC constraint development, MMMC environment setup, timing closure, advanced sign-off methodologies (OCV/AOCV/POCV), hierarchical timing analysis (ETM/ILM), scripting (Tcl/Python/Perl), physical design flows
Preferred skills
High-speed SerDes (112G/224G), Ethernet/PCIe/CXL PHY digital controller timing, analog/mixed-signal integration, ECO methodologies, DFT tools, SystemVerilog/Verilog, power-aware synthesis (UPF/CPF)
Technologies
Synopsys PrimeTime, Cadence Tempus, Synopsys/Cadence physical design toolchains, TSMC 5nm/3nm, Tcl, Python, Perl, SystemVerilog, Verilog
Responsibilities
Perform RTL synthesis and drive area/power/timing optimization for digital blocks; Author and validate SDC constraints including clock definitions and multi-mode exceptions; Set up and manage MMMC environments for PVT corner analysis; Drive timing closure from synthesis through sign-off; Define I/O timing budgets and interface constraints; Apply advanced sign-off methodologies including OCV/AOCV/POCV; Manage large-scale multi-corner/multi-mode STA runs with automation; Generate and validate timing ECOs; Partner with analog/RTL/verification teams for timing convergence; Collaborate on clock tree and power domain strategies.
Seniority
Senior, hands-on IC
