Principal Engineer, DFT
Core
Lead DFT architecture, implementation, and signoff for complex SoC/ASIC designs to ensure test coverage and manufacturing quality.
Role type
Principal Engineer, Design for Test (DFT)
Builds
SoC/ASIC chips for connectivity solutions (AI, cloud, 5G, data centers)
Domain
Semiconductor / ASIC Design / Test Engineering
Required skills
DFT methodologies, scan architecture, scan compression, ATPG, Memory BIST, Boundary Scan, Siemens EDA Tessent tools, synthesis and scan insertion tools, Static Timing Analysis (STA), SDC file management, timing closure, debugging
Preferred skills
technical leadership, mentorship, flow automation
Technologies
Siemens EDA Tessent, Synopsys Design Constraints (SDC)
Responsibilities
Define and drive DFT architecture and implementation strategies; Develop and implement scan, compression, MBIST, and other DFT features; Execute and support scan insertion, DFT verification, and ATPG flows; Collaborate with RTL, verification, physical design, and product engineering teams; Create and maintain DFT-related timing constraints and signoff requirements; Perform DFT timing analysis and debug timing-related issues; Drive DFT methodology improvements and contribute to flow automation; Provide technical leadership and mentorship to junior engineers
Seniority
Principal, hands-on IC with mentorship
