CareerPlan

Senior Physical Design Methodology Engineer, PPA Improvement Technology Scaling

US, CA, Santa ClaraFull-time$168k–$265k2026-10-28 → 2026-11-09

Core

Developing physical design methodologies and automation for graphics processors and SOCs to solve state-of-the-art physical design problems.

Role type

Senior Physical Design Methodology Engineer (PPA Scaling)

Builds

Graphics processors and System-on-Chips (SOCs)

Domain

Semiconductor / Hardware Design

Required skills

Physical Design Engineering, Floor Planning, Clock and Power Distribution, Place and Route, Timing Analysis and Closure, Power and Noise Analysis, Back-end Verification, Hierarchical Design, EDA Tools, Scripting (Perl, Python, C++)

Preferred skills

CPU Physical Design, Design for Yield and Manufacturability, EM and IR Closure, Thermal Management

Technologies

EDA tools, Perl, Python, C++