Formal Verification Engineer - New College Grad 2027
Core
Develop comprehensive formal verification test plans and environments to prove the correctness of next-generation chip RTL designs (CPU/GPU).
Role type
Junior IC formal verification engineer (RTL)
Builds
Verified RTL units for high-performance, low-power silicon chips
Domain
Semiconductor hardware design / Digital logic verification
Required skills
Formal verification techniques, HDLs (Verilog/System Verilog), CPU/GPU architecture knowledge, Temporal logic assertions, RTL debugging, Verification environment development, Test plan creation, Scripting for automation
Preferred skills
Experience with Formal Verification Tools (Jasper, IFV, SMV, SPIN), Abstraction techniques
Technologies
Verilog, System Verilog, Jasper, IFV, SMV, SPIN
Responsibilities
Develop comprehensive FV testplan documents, Create verification environments with assumptions and assertions, Apply FV techniques to prove design correctness, Debug RTL to identify failure scenarios, Develop automation scripts, Review formal setups and proofs
Seniority
Junior, entry-level (New College Grad 2027)
