Senior Verification Engineer - HSIO Unit Level
Core
Develop UVM-based verification test benches and methodologies for complex rapid data transfer IO IPs and sub-systems (USB, UFS, MPHY, Ethernet, MACSEC) within automotive chips.
Role type
Senior IC verification engineer (HSIO unit level)
Builds
Verification environments, testbenches, bus functional models, monitors, checkers, and scoreboards for high-speed I/Os and memory sub-systems.
Domain
Semiconductor / Automotive chips / High-speed I/Os
Required skills
UVM methodology, SystemVerilog, High Speed IO verification (UFS/PCIE/XUSB), Ethernet MAC/Switch knowledge, Functional coverage, Debugging and analytical skills
Preferred skills
AI tools for code development (Claude, Cursor), Formal verification, Automation
Technologies
SV, UVM, USB, UFS, MPHY, Ethernet, MACSEC, FPGA
Responsibilities
Architect testbenches and craft verification environments using SV and UVM; Define test plans and verification infrastructure; Build efficient and reusable bus functional models, monitors, checkers, and scoreboards; Implement functional coverage and coordinate verification closure; Collaborate with architects, designers, FPGA, and post-silicon teams.
Seniority
Senior, hands-on IC
