Responsable Vérification FPGA/ASIC - Spatial - Toulouse
Core
Lead functional verification strategy and planning for digital electronic designs based on FPGA/ASIC/SoC for next-generation satellite communication constellations.
Role type
Senior IC verification lead (FPGA/ASIC)
Builds
Digital electronic components for satellite communication systems
Domain
Aerospace / Space / Digital Electronics
Required skills
Functional verification strategy, Test plan definition, Test bench setup, Non-regression testing, VHDL, Verilog, SystemC, Linux, Scripting (Shell, Python), FPGA/ASIC/SoC architecture
Preferred skills
Experience with Xilinx, Microchip, Intel FPGAs, Standardized development cycles
Technologies
VHDL, Verilog, SystemC, Linux, Shell, Python, Xilinx, Microchip, Intel
Responsibilities
Define global verification strategy and planning, Write high-level test plans, Organize verification activities (test benches, validation campaigns), Review unit test plans, Track verification progress
Seniority
Senior, hands-on IC
