Senior Verification Engineer
Core
Develop and own verification strategies, environments, and tests for complex IP and subsystems including high-speed I/O, PCIe, DDR, and security IP for next-generation SoCs.
Role type
Senior IC verification engineer (IP/Subsystem)
Builds
Reusable SystemVerilog/UVM verification environments, agents, scoreboards, and production-ready IP for SoC integration
Domain
Semiconductor hardware design, IP verification, SoC integration
Required skills
SystemVerilog, UVM, digital design (Verilog/RTL), functional coverage, assertions, debug, Python/TCL/Bash/C++, SoC architecture, clock/reset management
Preferred skills
PCIe controllers, DDR controllers, high-speed serial interfaces, security IP, formal verification, emulation, low-power verification (UPF), ARM architectures
Technologies
SystemVerilog, UVM, Python, Perl, TCL, Bash, C, C++, PCIe, DDR, AXI, AHB, APB, CHI, UPF
Responsibilities
Develop verification strategies and test plans; build reusable verification environments and components; drive functional, code, assertion, and scenario coverage to closure; debug failures across RTL, testbench, firmware, and system interactions; mentor engineers and improve verification methodologies
Seniority
Senior, hands-on IC