SoC Design Verification Engineer
Core
Design Verification Engineer for Apple's flagship Cellular 5G SoCs, focusing on integrating IP-level DV environments and improving tape-out readiness.
Role type
Senior IC SoC Design Verification Engineer
Builds
Cellular 5G SoCs and high-speed layered protocol implementations
Domain
Semiconductor / SoC Design / 5G Cellular
Required skills
SystemVerilog, UVM, coverage-driven verification, OOP (C++, Python, Java), digital design, high-speed protocols, memory controllers, low-power architecture
Preferred skills
MSEE/MSCS, computer architecture, networking protocols, HVL, reference model development
Technologies
UVM, SystemVerilog, Python, C++, Java, PCIe, DDR, USB, SPI, I2C, UART
Responsibilities
Build coverage-driven verification plans from specifications; Create IP level module and sub-system verification plans, testbenches, and test infrastructure; Architect UVM-based reusable testbenches integrating multi-instance VIPs to SoC level; Collaborate with design, architecture, SW, FW, and external IP teams to verify overall SoC design; Work with DV methodology architects to improve verification flow.
Seniority
Senior, hands-on IC
