FPGA IP Solution Design & Verification Engineer
Core
Design, develop, and verify high-quality FPGA IP solutions for Altera's leading-edge FPGA devices across the full lifecycle.
Role type
Senior IC FPGA IP Solution Design & Verification Engineer
Builds
Reusable IP blocks, subsystems, and FPGA-based platform images
Domain
Semiconductor / FPGA / Digital IC Design
Required skills
RTL design (Verilog/SystemVerilog), FPGA architecture, UVM/SystemVerilog Assertions, Python/Perl/Tcl scripting, protocol stack integration (Ethernet/PCIe/DDR/AXI), hardware bring-up, timing/power optimization
Preferred skills
Cross-functional collaboration, root cause analysis, documentation
Technologies
Quartus Prime, Vivado, Oscilloscopes, Logic Analyzers, Protocol Analyzers
Responsibilities
Develop FPGA logic designs and RTL code; Create behavioral and RTL models; Design and maintain verification environments and testbenches; Integrate and debug protocol stacks (Ethernet MAC, PCS/PMA); Bring up and validate designs on hardware; Perform platform-level debug using observability tools; Document design decisions and verification results
Seniority
Mid-level, hands-on IC
