Senior Digital Verification Engineer
Core
Design and implement verification environments, checkers, and testbenches in System Verilog for edge AI hardware IP (NPUs, Vision DSPs) and system-level solutions.
Role type
Senior Digital Verification Engineer (Hardware IP)
Builds
Verification environments and testbenches for Neural Network Processors and Vision DSPs
Domain
Semiconductor / Hardware IP / Edge AI
Deliverable
production ML models
Required skills
System Verilog, UVM, verification strategy, functional coverage, test plan design, complex problem analysis
Preferred skills
Architecture definition, verification sign-off, agile flow adaptation
Technologies
System Verilog, UVM
Responsibilities
Design verification environments, checkers, and testbenches; develop verification strategies and functional coverage plans; contribute to advanced verification sign-off processes
Seniority
Senior, hands-on IC
