Senior Engineer, DPG LPDDR Verification
Core
Lead verification and end-to-end analysis of sophisticated full-chip gate-level custom designs for advanced low-power and power management technologies (DDR5, LPDDR5, DDR6, LPDDR6) operating at high speeds up to 9600MT/s.
Role type
Senior IC verification engineer (memory/DRAM)
Builds
Pre-silicon full chip designs for DRAM and emerging memory architectures
Domain
Semiconductor / Memory / Digital Logic
Deliverable
production ML models
Required skills
System Verilog, UVM Test Bench, PLI coding, Gate-level simulation (with delays), Logic schematic analysis, CMOS circuit design analysis, Timing analysis (Setup/Hold, critical data path), AI-assisted verification tools
Preferred skills
Experience with DDR/SRAM memory architectures, AI-based automation for verification productivity
Technologies
Verilog, System Verilog, UVM, Simulation tools, AI-assisted tools
Responsibilities
Guide and set direction for verification efforts; Simulate, analyze, and debug pre-silicon full chip designs; Develop test cases/stimulus to increase functional coverage; Participate in developing verification methodology and environments; Co-work on developing new verification flows; Develop and maintain test benches/vectors and run regressions; Identify verification problems suitable for AI-based automation.
Seniority
Senior, hands-on IC
