Formal Verification Engineer - New College Grad 2027
Core
Develop comprehensive formal verification test plans and environments to prove the correctness of next-generation chip RTL designs.
Role type
Junior IC formal verification engineer (RTL)
Builds
Next-generation CPU/GPU silicon designs
Domain
Semiconductor hardware design
Required skills
Formal verification techniques, Verilog/System Verilog, CPU/GPU architecture knowledge, Temporal logic assertions, RTL debugging, Verification environment development, Test plan creation, Scripting for automation
Preferred skills
Experience with Formal Verification Tools (Jasper, IFV, SMV, SPIN), Abstraction techniques
