Principal Design Verification Engineer- SerDes/PHY IP
Core
Architect and execute functional verification for high-speed SerDes/PHY IP (PMA, PCS, PHY-MAC) powering rack-scale AI infrastructure.
Role type
Principal Design Verification Engineer (SerDes/PHY IP)
Builds
High-speed serial link blocks (UALink, UCIe, PCIe Gen 6/7, Ethernet) for AI platforms
Domain
Semiconductor IP, High-Speed Serial Interfaces, AI Infrastructure
Deliverable
production ML models
Required skills
SystemVerilog, UVM, Analog/Mixed-Signal Co-simulation, Real Number Modeling (RNM), Coverage Closure, Debugging, Protocol Verification
Preferred skills
MS/PhD in EE/CE, Emulation Platform Experience, Python/Perl Scripting, Post-Silicon Bring-up
Technologies
SystemVerilog, UVM, Palladium, Veloce, ZeBu, PCIe Gen 6/7, UALink, UCIe, Ethernet
Responsibilities
Architect UVM-based verification environments; Develop SystemVerilog/UVM testbenches and reference models; Execute functional and corner-case verification; Lead coverage analysis and closure; Mentor junior DV engineers; Collaborate with analog/AMS designers on RNM and behavioral models.
Seniority
Principal, hands-on IC with technical leadership
