Design Verification Engineer, New Grad
Core
Design Verification Engineer for SambaNova's RDU (Reconfigurable Dataflow Unit) chip, building SystemVerilog and UVM environments to verify chip-level control, initialization, sequencing, and state transitions.
Role type
New Grad Design Verification Engineer (IC)
Builds
SystemVerilog and UVM testbenches, sequences, checkers, assertions, and functional coverage for AI inference chips
Domain
Semiconductor / AI Infrastructure / Hardware Verification
Deliverable
production ML models
Required skills
SystemVerilog, UVM, constrained-random verification, functional coverage, assertions, clock domain crossing, Python scripting, digital design, computer architecture
Preferred skills
AI tools for verification, internship in design verification
Technologies
SystemVerilog, UVM, Python, Perl, TCL, shell
Responsibilities
Write and execute verification plans for chip-level control and initialization features; Build SystemVerilog and UVM testbench components including sequences, checkers, and assertions; Write directed and constrained-random tests to find corner cases; Debug simulation and regression failures with RTL designers; Analyze functional and code coverage and close coverage gaps
Seniority
New Grad, hands-on IC
